library IEEE;
use IEEE.std_logic_1164.all;

entity mealy is
	port(
		clk    : in  std_logic;
		rst    : in  std_logic;
		s_in  : in  std_logic;
		d_out : out std_logic
	);
end entity mealy;

architecture implementation of mealy is
	type state_type is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15);
	signal state, next_state : state_type;

begin
	combiantiorial : process(s_in, state, next_state)
	begin
		case (state) is
			when s0 => if (s_in = '0') then
					next_state <= s1;
					d_out     <= '0';
				else
					next_state <= s0;
					d_out     <= '0';
				end if;
			when s1 => if (s_in = '0') then
					next_state <= s2;
					d_out     <= '0';
				else
					next_state <= s0;
					d_out     <= '0';
				end if;
			when s2 => if (s_in = '0') then
					next_state <= s3;
					d_out     <= '0';
				else
					next_state <= s0;
					d_out     <= '0';
				end if;
			when s3 => if (s_in = '0') then
					next_state <= s4;
					d_out     <= '0';
				else
					next_state <= s0;
					d_out     <= '0';
				end if;
			when s4 => if (s_in = '0') then
					next_state <= s5;
					d_out     <= '0';
				else
					next_state <= s0;
					d_out     <= '0';
				end if;
			when s5 => if (s_in = '0') then
					next_state <= s6;
					d_out     <= '0';
				else
					next_state <= s0;
					d_out     <= '0';
				end if;
			when s6 => if (s_in = '0') then
					next_state <= s6;
					d_out     <= '0';
				else
					next_state <= s7;
					d_out     <= '0';
				end if;
			when s7 => if (s_in = '0') then
					next_state <= s0;
					d_out     <= '0';
				else
					next_state <= s8;
					d_out     <= '0';
				end if;
			when s8 => if (s_in = '0') then
					next_state <= s9;
					d_out     <= '0';
				else
					next_state <= s0;
					d_out     <= '0';
				end if;
			when s9 => if (s_in = '0') then
					next_state <= s10;
					d_out     <= '0';
				else
					next_state <= s0;
					d_out     <= '0';
				end if;
			when s10 => if (s_in = '0') then
					next_state <= s11;
					d_out     <= '0';
				else
					next_state <= s0;
					d_out     <= '0';
				end if;
			when s11 => if (s_in = '0') then
					next_state <= s12;
					d_out     <= '0';
				else
					next_state <= s0;
					d_out     <= '0';
				end if;
			when s12 => if (s_in = '0') then
					next_state <= s5;
					d_out     <= '0';
				else
					next_state <= s13;
					d_out     <= '0';
				end if;
			when s13 => if (s_in = '0') then
					next_state <= s14;
					d_out     <= '0';
				else
					next_state <= s0;
					d_out     <= '0';
				end if;
			when s14 => if (s_in = '0') then
					next_state <= s15;
					d_out     <= '0';
				else
					next_state <= s0;
					d_out     <= '0';
				end if;
			when s15 => if (s_in = '0') then
					next_state <= s3;
					d_out     <= '0';
				else
					next_state <= s0;
					d_out     <= '1';
				end if;
		end case;
	end process;
end implementation;